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| Game title |
Version |
Latest Report |
Message |
| SplinterCell |
v1.13.2 |
2022-09-28 |
Branch in Jump delay slot at 04285434 in block starting at 04285430 |
| SplinterCell |
v1.13.2 |
2022-09-28 |
Branch in Jump delay slot at 04285430 in block starting at 04285430 |
| SplinterCell |
v1.13.2 |
2022-09-28 |
Branch in Jump delay slot at 09ffe2c8 in block starting at 09ffe2b4 |
| SplinterCell |
v1.13.2 |
2022-09-28 |
MIPSCompileOp: Invalid instruction 00000235 |
| SplinterCell |
v1.13.2 |
2022-09-28 |
Jump to invalid address: 0deb9884 |
| SplinterCell |
v1.13.1-205-g8478a8c86 |
2022-09-26 |
Error in shader compilation: info: ERROR: 0:21: Incompatible types in initialization (and no available implicit conversion)
ERROR: 0:25: Use of undeclared identifier 'tsize'
ERROR: 0:27: Use of undeclared identifier 'tsize'
00000000:000003e2 Tex TexAlpha Depal TClampST TFuncMod
#version 300 es
#extension GL_EXT_shader_framebuffer_fetch : require
// Apple A11 GPU - GLSL 300
#define DISCARD discard
precision lowp float;
precision highp int;
#define splat3(x) vec3(x)
#define mul(x, y) ((x) * (y))
precision highp int;
uniform sampler2D tex;
uniform vec4 u_texclamp;
uniform sampler2D pal;
uniform uint u_depal_mask_shift_off_fmt;
in lowp vec4 v_color0;
in mediump vec3 v_texcoord;
out vec4 fragColor0;
void main() {
vec2 fixedcoord = vec2(clamp(v_texcoord.x, u_texclamp.z, u_texclamp.x - u_texclamp.z), clamp(v_texcoord.y, u_texclamp.w, u_texclamp.y - u_texclamp.w));
vec2 uv = fixedcoord.xy;
vec2 uv_round;
vec2 tsize = textureSize(tex, 0).xy;
vec2 fraction;
bool bilinear = (u_depal_mask_shift_off_fmt >> 31) != 0U;
if (bilinear) {
uv_round = uv * tsize - vec2(0.5, 0.5);
fraction = fract(uv_round);
uv_round = (uv_round - fraction + vec2(0.5, 0.5)) / tsize;
} else {
uv_round = uv;
}
highp vec4 t = texture(tex, uv_round);
highp vec4 t1 = textureOffset(tex, uv_round, ivec2(1, 0));
highp vec4 t2 = textureOffset(tex, uv_round, ivec2(0, 1));
highp vec4 t3 = textureOffset(tex, uv_round, ivec2(1, 1));
uint depalMask = (u_depal_mask_shift_off_fmt & 0xFFU);
uint depalShift = (u_depal_mask_shift_off_fmt >> 8) & 0xFFU;
uint depalOffset = ((u_depal_mask_shift_off_fmt >> 16) & 0xFFU) << 4;
uint depalFmt = (u_depal_mask_shift_off_fmt >> 24) & 0x3U;
uvec4 col; uint index0; uint index1; uint index2; uint index3;
switch (int(depalFmt)) {
case 0:
col = uvec4(t.rgb * vec3(31.99, 63.99, 31.99), 0);
index0 = (col.b << 11) | (col.g << 5) | (col.r);
if (bilinear) {
col = uvec4(t1.rgb * vec3(31.99, 63.99, 31.99), 0);
index1 = (col.b << 11) | (col.g << 5) | (col.r);
col = uvec4(t2.rgb * vec3(31.99, 63.99, 31.99), 0);
index2 = (col.b << 11) | (col.g << 5) | (col.r);
col = uvec4(t3.rgb * vec3(31.99, 63.99, 31.99), 0);
index3 = (col.b << 11) | (col.g << 5) | (col.r);
}
break;
case 1:
col = uvec4(t.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index0 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index1 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
col = uvec4(t2.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index2 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
col = uvec4(t3.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index3 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
}
break;
case 2:
col = uvec4(t.rgba * 15.99);
index0 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * 15.99);
index1 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
col = uvec4(t2.rgba * 15.99);
index2 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
col = uvec4(t3.rgba * 15.99);
index3 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
}
break;
case 3:
col = uvec4(t.rgba * 255.99);
index0 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * 255.99);
index1 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
col = uvec4(t2.rgba * 255.99);
index2 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
col = uvec4(t3.rgba * 255.99);
index3 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
}
break;
};
index0 = ((index0 >> depalShift) & depalMask) | depalOffset;
t = texelFetch(pal, ivec2(index0, 0), 0);
if (bilinear && !(index0 == index1 && index1 == index2 && index2 == index3)) {
index1 = ((index1 >> depalShift) & depalMask) | depalOffset;
index2 = ((index2 >> depalShift) & |
| SplinterCell |
v1.13.1-205-g8478a8c86 |
2022-09-26 |
Error in shader compilation: info: ERROR: 0:21: Incompatible types in initialization (and no available implicit conversion)
ERROR: 0:25: Use of undeclared identifier 'tsize'
ERROR: 0:27: Use of undeclared identifier 'tsize'
00000000:000003c2 Tex Depal TClampST TFuncMod
#version 300 es
#extension GL_EXT_shader_framebuffer_fetch : require
// Apple A11 GPU - GLSL 300
#define DISCARD discard
precision lowp float;
precision highp int;
#define splat3(x) vec3(x)
#define mul(x, y) ((x) * (y))
precision highp int;
uniform sampler2D tex;
uniform vec4 u_texclamp;
uniform sampler2D pal;
uniform uint u_depal_mask_shift_off_fmt;
in lowp vec4 v_color0;
in mediump vec3 v_texcoord;
out vec4 fragColor0;
void main() {
vec2 fixedcoord = vec2(clamp(v_texcoord.x, u_texclamp.z, u_texclamp.x - u_texclamp.z), clamp(v_texcoord.y, u_texclamp.w, u_texclamp.y - u_texclamp.w));
vec2 uv = fixedcoord.xy;
vec2 uv_round;
vec2 tsize = textureSize(tex, 0).xy;
vec2 fraction;
bool bilinear = (u_depal_mask_shift_off_fmt >> 31) != 0U;
if (bilinear) {
uv_round = uv * tsize - vec2(0.5, 0.5);
fraction = fract(uv_round);
uv_round = (uv_round - fraction + vec2(0.5, 0.5)) / tsize;
} else {
uv_round = uv;
}
highp vec4 t = texture(tex, uv_round);
highp vec4 t1 = textureOffset(tex, uv_round, ivec2(1, 0));
highp vec4 t2 = textureOffset(tex, uv_round, ivec2(0, 1));
highp vec4 t3 = textureOffset(tex, uv_round, ivec2(1, 1));
uint depalMask = (u_depal_mask_shift_off_fmt & 0xFFU);
uint depalShift = (u_depal_mask_shift_off_fmt >> 8) & 0xFFU;
uint depalOffset = ((u_depal_mask_shift_off_fmt >> 16) & 0xFFU) << 4;
uint depalFmt = (u_depal_mask_shift_off_fmt >> 24) & 0x3U;
uvec4 col; uint index0; uint index1; uint index2; uint index3;
switch (int(depalFmt)) {
case 0:
col = uvec4(t.rgb * vec3(31.99, 63.99, 31.99), 0);
index0 = (col.b << 11) | (col.g << 5) | (col.r);
if (bilinear) {
col = uvec4(t1.rgb * vec3(31.99, 63.99, 31.99), 0);
index1 = (col.b << 11) | (col.g << 5) | (col.r);
col = uvec4(t2.rgb * vec3(31.99, 63.99, 31.99), 0);
index2 = (col.b << 11) | (col.g << 5) | (col.r);
col = uvec4(t3.rgb * vec3(31.99, 63.99, 31.99), 0);
index3 = (col.b << 11) | (col.g << 5) | (col.r);
}
break;
case 1:
col = uvec4(t.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index0 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index1 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
col = uvec4(t2.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index2 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
col = uvec4(t3.rgba * vec4(31.99, 31.99, 31.99, 1.0));
index3 = (col.a << 15) | (col.b << 10) | (col.g << 5) | (col.r);
}
break;
case 2:
col = uvec4(t.rgba * 15.99);
index0 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * 15.99);
index1 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
col = uvec4(t2.rgba * 15.99);
index2 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
col = uvec4(t3.rgba * 15.99);
index3 = (col.a << 12) | (col.b << 8) | (col.g << 4) | (col.r);
}
break;
case 3:
col = uvec4(t.rgba * 255.99);
index0 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
if (bilinear) {
col = uvec4(t1.rgba * 255.99);
index1 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
col = uvec4(t2.rgba * 255.99);
index2 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
col = uvec4(t3.rgba * 255.99);
index3 = (col.a << 24) | (col.b << 16) | (col.g << 8) | (col.r);
}
break;
};
index0 = ((index0 >> depalShift) & depalMask) | depalOffset;
t = texelFetch(pal, ivec2(index0, 0), 0);
if (bilinear && !(index0 == index1 && index1 == index2 && index2 == index3)) {
index1 = ((index1 >> depalShift) & depalMask) | depalOffset;
index2 = ((index2 >> depalShift) & depalMask |
| SplinterCell |
v1.13.2 |
2022-09-22 |
ReadFromHardware: Invalid address 0a000000 near PC 0880501c LR 0880501c |
| SplinterCell |
v1.13.2 |
2022-09-18 |
MIPSCompileOp: Invalid instruction 001fba1e |
| SplinterCell |
v1.13.1 |
2022-09-13 |
MIPSCompileOp: Invalid instruction 9e599e59 |
| SplinterCell |
v1.13.1 |
2022-09-13 |
MIPSCompileOp: Invalid instruction 9e590000 |
| SplinterCell |
v1.13.1 |
2022-09-13 |
MIPSCompileOp: Invalid instruction 0000fe7a |
| SplinterCell |
v1.10.2 |
2022-09-09 |
sceDmacMemcpy(dest=097a3c50, src=040c8900, size=32768): overlapping read |
| SplinterCell |
v1.10.2 |
2022-09-09 |
sceDmacMemcpy(dest=0872a700, src=08732700, size=32768): overlapping read |
| SplinterCell |
v1.10.2 |
2022-09-09 |
Jump to invalid address: 04f72900 |
| SplinterCell |
v1.10.2 |
2022-09-07 |
MIPSCompileOp: Invalid instruction 000417fa |
| SplinterCell |
v1.13.1 |
2022-08-27 |
Jump to invalid address: 05cb7340 |
| SplinterCell |
v1.13.1 |
2022-08-22 |
Unexpected mpeg first timestamp: 7f2b8ff242d / 8739067208749 |
| SplinterCell |
v1.13.1 |
2022-08-06 |
Unknown GetPointer 00000000 PC 00000000 LR 08aa2048 |
| SplinterCell |
v1.13.1 |
2022-08-06 |
ReadFromHardware: Invalid address 00000000 near PC 00000000 LR 08aa2048 |
| SplinterCell |
v1.12.3 |
2022-08-02 |
sceKernelLoadModule: unsupported options size=00000014, flags=08c98210, pos=0, access=1, data=2, text=2 |
| SplinterCell |
v1.12.3 |
2022-08-02 |
sceKernelLoadModule: unsupported options size=00000014, flags=08caf9fc, pos=0, access=1, data=1, text=1 |
| SplinterCell |
v1.12.3 |
2022-07-31 |
sceDmacMemcpy(dest=0874e580, src=08756580, size=32768): overlapping read |
| SplinterCell |
v1.9.4 |
2022-07-22 |
MIPSCompileOp: Invalid instruction 0002401f |
| SplinterCell |
v1.9.4 |
2022-07-22 |
MIPSCompileOp: Invalid instruction 0004e41f |
| SplinterCell |
v1.10-6-g8ac4efd3c |
2022-07-18 |
Ignoring func export sceMp3/7f696782, already implemented in HLE. |
| SplinterCell |
v1.10-6-g8ac4efd3c |
2022-07-18 |
Ignoring func export sceMp3/44e07129, already implemented in HLE. |
| SplinterCell |
v1.10-6-g8ac4efd3c |
2022-07-18 |
Ignoring func export sceMp3/3cef484f, already implemented in HLE. |
| SplinterCell |
v1.10-6-g8ac4efd3c |
2022-07-18 |
Ignoring func export sceMp3/3c2fa058, already implemented in HLE. |
| SplinterCell |
v1.7.1 |
2022-07-17 |
MIPSCompileOp: Invalid instruction 0000079e |
| SplinterCell |
v1.12.3 |
2022-07-15 |
MIPSCompileOp: Invalid instruction 000d9c54 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-14 |
Jump to invalid address: 06325440 PC 09ffe2dc LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-14 |
Jump to invalid address: 053a23c0 PC 09ffe2cc LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-14 |
Jump to invalid address: 02146c10 PC 09ffe298 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-14 |
Jump to invalid address: 053a2100 PC 09ffe268 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-15 |
sceDmacMemcpy(dest=0872f7a0, src=087377a0, size=32768): overlapping read |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 05e17b50 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
MIPSCompileOp: Invalid instruction 43f5ff56 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 03f1f818 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 063b4bc0 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 03d82fd0 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 061e2b50 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 03827160 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
MIPSCompileOp: Invalid instruction 43f593e8 |
| SplinterCell |
v1.12.3 |
2022-07-09 |
Jump to invalid address: 05cb7340 PC 09ffe2b8 LR 09ffe260 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
Jump to invalid address: 03217680 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
MIPSCompileOp: Invalid instruction 00010839 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
sceDmacMemcpy(dest=08733800, src=0873b800, size=32768): overlapping read |
| SplinterCell |
v1.11.3 |
2022-07-09 |
Jump to invalid address: 05519980 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
Jump to invalid address: 04aeb1c0 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
Jump to invalid address: 0530b840 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 0644e340 PC 09ffe2c4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 03d401e0 PC 09ffe2c0 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 03eca2d8 PC 09ffe2b8 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 0644e340 PC 09ffe2b4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 03d3fd90 PC 09ffe2b0 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 06258ed0 PC 09ffe2a4 LR 09ffe260 |
| SplinterCell |
v1.11.3 |
2022-07-09 |
Jump to invalid address: 05b9b040 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
Jump to invalid address: 05c5f380 PC 09ffe2dc LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
Jump to invalid address: 04fa2dc0 PC 09ffe2cc LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
Jump to invalid address: 07ff9300 PC 09ffe2b4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
MIPSCompileOp: Invalid instruction 000138e9 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
MIPSCompileOp: Invalid instruction 00234a85 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-07-07 |
Jump to invalid address: 04fa2d00 PC 09ffe268 LR 09ffe260 |
| SplinterCell |
v1.12.3 |
2022-07-05 |
Jump to invalid address: 025fd500 |
| SplinterCell |
v1.9.4 |
2022-07-04 |
ReadFromHardware: Invalid address ffffffff near PC ffffffff LR 089229c0 |
| SplinterCell |
v1.12.3 |
2022-07-02 |
MIPSCompileOp: Invalid instruction 000046d5 |
| SplinterCell |
v1.12.3 |
2022-07-02 |
MIPSCompileOp: Invalid instruction 000424d4 |
| SplinterCell |
v1.12.3 |
2022-07-02 |
MIPSCompileOp: Invalid instruction 0008f13f |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-30 |
MIPSCompileOp: Invalid instruction 000055fa |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-30 |
MIPSCompileOp: Invalid instruction 0006dd78 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-30 |
Jump to invalid address: 07ff9100 PC 09ffe268 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-30 |
MIPSCompileOp: Invalid instruction 0000fe3d |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
MIPSCompileOp: Invalid instruction 0002590e |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
MIPSCompileOp: Invalid instruction 0049ed7b |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
MIPSCompileOp: Invalid instruction 00051d0e |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
MIPSCompileOp: Invalid instruction 004ac6bf |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 03efe630 PC 09ffe2c8 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 05ced140 PC 09ffe2c4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 03cd4320 PC 09ffe2c0 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 07ff8f80 PC 09ffe2bc LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 03e50598 PC 09ffe2b8 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 05ced140 PC 09ffe2b4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 03cd3ed0 PC 09ffe2b0 LR 09ffe260 |
| SplinterCell |
v1.12.3-1315-gdd6c35b68 |
2022-06-28 |
Jump to invalid address: 05b12e10 PC 09ffe2a4 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 02f5c960 PC 09ffe294 LR 09ffe260 |
| SplinterCell |
v1.12.3-1358-gdca637d8d |
2022-07-09 |
Jump to invalid address: 07ff9250 PC 09ffe290 LR 09ffe260 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
MIPSCompileOp: Invalid instruction 0031bc35 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 07ff9130 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 04d37000 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 0712f270 |
| SplinterCell |
v1.11.3 |
2022-07-10 |
Jump to invalid address: 061dc880 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
MIPSCompileOp: Invalid instruction 4359824d |
| SplinterCell |
v1.11.3 |
2022-06-26 |
MIPSCompileOp: Invalid instruction 435a5940 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
MIPSCompileOp: Invalid instruction 0000097d |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 0534a040 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 039dffd0 |
| SplinterCell |
v1.11.3 |
2022-06-26 |
Jump to invalid address: 0534a100 |
| SplinterCell |
v1.12.3 |
2022-06-25 |
sceDmacMemcpy(dest=0873db60, src=08745b60, size=32768): overlapping read |
| SplinterCell |
v1.12.3 |
2022-06-23 |
MIPSCompileOp: Invalid instruction 00000838 |